Hardware Engineer · Researcher · Educator

Venkata
Sriram K.

M.S. ECE — Portland State University B.Tech ECE - JNTU, Hyderabad
RTL Design & Verification
Embedded Systems
Hardware for AI/ML
Circuit Modeling and Verification
Analog and Mixed Signal

A research-oriented engineer who thrives at the intersection of silicon and systems — designing circuits, building hardware from the ground up, verifying it rigorously, and genuinely passionate about teaching every step of the way.

View Projects Get In Touch Resume PDF
Venkata Sriram Kamarajugadda
10+
Hardware Builds
6
Publications
1M+
Logic Gates
Silicon Heartbeat — RTL Data Path
D Q
Engineer by the day, Maker by the night
01 — Featured Projects

Hardware builds & implementations

Research / Hardware for AI-ML
Chiplet-Based Reservoir Computing Accelerator

Structured-sparse hardware accelerator for efficient reservoir state update in streaming inference. Exploring next-gen AI compute paradigms via Echo State Networks.

ChipletESNSparse MatricesStreaming Inference
View Research (Github) →
FPGA (Hw/SW Co-Design)
Audio Delay System — RVfpga

FPGA-based audio delay system on Nexys A7 using VeeRwolf RISC-V architecture via the RVfpga platform. Full hardware-software co-design.

RISC-VNexys A7VeeRwolfRVfpgaI2S2Delay Line RTL
GitHub →
UVM
UVM Verification of ALU

Complete UVM-based functional verification environment for an ALU. Includes driver, monitor, scoreboard, and coverage groups with constrained-random stimulus generation.

UVMSystemVerilogQuestaSimCoverage
GitHub →
UVM
UVM Verification of MAC Unit (Matrix 3×3)

UVM testbench targeting a 3×3 MAC (Multiply-Accumulate) matrix unit. Verifies data path integrity, accumulation correctness, and edge-case arithmetic behavior.

UVMMACSystemVerilogScoreboard
GitHub →
SystemVerilog (Design & Verification)
SV Design & Class-Based Verification of UART Protocol

RTL design of UART Tx/Rx in SystemVerilog with a full class-based verification environment. Covers baud rate, start/stop bits, parity, and error injection testing.

SystemVerilogUARTClass-Based TBProtocol
GitHub →
Verilog
Synchronous FIFO & Round Robin Arbiter

Verilog RTL design of a parameterized synchronous FIFO with full/empty flags and a round-robin arbiter for fair multi-master bus arbitration. Both simulation verified.

VerilogFIFOArbiterRTL
GitHub →
View all projects built by me →
02 — Research

Current & ongoing investigations

01
Active
Hardware Accelerator for Reservoir State Update in Echo State Networks

Chiplet-based accelerator targeting energy-efficient edge inference via Echo State Networks. Explores structured sparsity in reservoir state computations to reduce memory bandwidth and compute overhead in real-time streaming workloads.

Portland State University · Hardware AI Accelerators · 2026–Present
02
Paused
Mutation-Aided RTL Design of a 4-Phase Code Generator for Low-Correlation Spread Spectrum Sequences

MGA Algorithm project exploring genetic/mutation-based RTL design methodology to synthesize polyphase code generators optimized for low cross-correlation in spread spectrum communications.

MGIT / PSU · RTL Synthesis · Digital Comms · Revisiting later
03 — Skills

Tools, languages & expertise

RTL & HDL
Verilog HDL
95%
SystemVerilog
85%
UVM
80%
VHDL
55%
Architecture & Design
Computer Architecture
88%
Embedded Systems
78%
Hardware for AI/ML
82%
FPGA Design
85%
Circuit Modelling & Verif.
75%
Programming
Python
80%
C / C++
70%
RISC-V ALP
65%
EDA & Simulation Tools
VivadoQuestaSimModelSim Synopsys VCSLTSpiceEDA Playground PlatformIOVS Code
Other
PCB DesignIoT OpenCVPyTorch 3D Printing & Prototyping
FPGA Boards
Digilent ZyboNexys A7 Basys 3 (Artix-7)terasIC DE10-Lite Vicharak Shrike-LiteSoan-Papdi terasIC DE2i-150
Dev Boards & MCUs
Arduino UnoArduino Mega Arduino GigaESP8266 ESP32ESP32-S2 STM32RPi Pico RPi 4
04 — Publications

Papers & technical writing

Conference Proceeding
Awaiting Publication
Signal Design for LPI Radar
S P Singh, A K Singh, Anupam Sharma, Ravi Paul Gollapalli, Venkata Sriram Kamarajugadda
ICASPACE-2025 (in association with Springer)
Paper presented (Jan 2025). Proceedings currently being published.
Article Series — LinkedIn
Ongoing
Latest Articles
Venkata Sriram Kamarajugadda
LinkedIn Article Series
View All Articles →
Peer-Reviewed Journal
Published
Mutation-Aided RTL Design of a Four-Phase Code Generator for Low-Correlation Spread Spectrum Sequences
Venkata Sriram Kamarajugadda, Dharmapuri Jayanth, Karra Vinay Reddy, Kovai Preetham Kumar, Dr S P Singh
JETIR Volume 12, Issue 5, May 2025
View Paper →
Peer-Reviewed Journal
Published
Unsupervised Deep Learning Approach for Detection of Anomalies in Hyperspectral images
Thokala Brundha, Venkata Sriram Kamarajugadda, Y.Pavan Narsimha Rao, A. Ratna Raju
IJRAR Volume 12, Issue 2, May 2025
View Paper →
Peer-Reviewed Journal
Published
GARUDA: Ground and Aerial Reconnaissance Unit for Defense and Assistance for Defense and Disaster Response Applications
Venkata Sriram Kamarajugadda, Anoop Dorepally, Thokala Brundha
The Academic: Int. Journal for Multidisciplinary Research, Vol 2, Issue 12, Dec 2024
View Paper →
Seminar Presentation
Published
AI & IoT Driven Disaster Management System for Indian Defense Applications
Venkata Sriram Kamarajugadda, Anoop Dorepally, Thokala Brundha, A Bala Raju
All India Seminar on "Role of AI in Tech Advancements in Aerospace and Defence", The Institution of Engineers (India)
Paper presented at the seminar.
05 — Teaching

Education & community

Hardware, Explained — LinkedIn Series

Written article series making hardware design concepts approachable for students and professionals transitioning into VLSI, FPGA, and AI chip roles.

Read Series →
YouTube Channel

Hardware Explained — Coming soon. Comprehensive video deep-dives into Digital Design, VLSI, and a dedicated Verilog Learning Course.

Coming Soon →
Workshops & Webinars

Conducted 12+ workshops & webinars (and counting) in the fields of Basic Electronics, IoT, PCB Designing, OpenCV, and Digital Design (VLSI).

The Hardware Community

Building Soon — An open-source platform for students to find, build, and learn cutting-edge hardware projects from first principles.

Coming Soon →
06 — Blog / Writing

Hardware, Explained

Hardware, Explained · Issue 01
What is an HDL and Why both VLSI and Embedded Engineers should learn it?

Understanding the importance of Hardware Description Languages bridging the gap between VLSI and Embedded Systems.
Hardware, Explained · Issue 02
Did you know hardware thinks in parallel (software doesnt)?

Exploring the fundamental difference in execution paradigms between hardware design and traditional software programming.
Hardware, Explained · Issue 03
Why do we need a clock in hardware?

A deep dive into synchronous digital design and the critical role of clock signals in coordinating hardware operations.
Hardware, Explained · Issue 04
Most HDL beginners are writing software. And Thats the problem.

Addressing common pitfalls when transitioning to HDL and why thinking in hardware is essential for efficient RTL design.
07 — Contact

Let's connect

Open to research collaborations, industry opportunities in VLSI / FPGA / AI hardware, and conversations about teaching electronics. Based in Portland, OR.

github.com/kvsriram11 linkedin.com/in/venkata-sriram-kamarajugadda instagram.com/hardware.explained YouTube Channel (coming soon)